Referring to FIG. 1, an example of a conventional phase locked loop circuit 10 is shown. The circuit 10 generally comprises phase frequency detector 12, a charge pump/filter 14, a clamp 15, an oscillator 16 and a divider 18. The circuit 10 is used to multiply a reference signal REFCLK having a fixed frequency, received at an input 24, by some multiple set by the divider 18. The phase frequency detector 12 is coupled to the oscillator 16 through the charge pump/filter 14. The divider circuit 18 has an input 28 that receives a feedback of the signal VCO_OUT presented at an output 29 of the oscillator 16. The divider 18 presents a signal to the input 30 of the phase frequency detector 12. The phase frequency detector 12 is capable of indicating both phase error and frequency error. Errors coupled through the charge pump/filter 14 cause the VCO 16 to change the frequency of the signal VCO_OUT to minimize the error. VCO frequency errors may be managed by the circuit 10. The nominal frequency of operation of the signal VCO_OUT will be the frequency of the reference signal REFCLK multiplied by the divider ratio. A typical phase frequency detector 12, as used in the circuit 10, cannot tolerate irregular input data streams that may be found in a serial data input. As a result, the circuit 10 may not be an adequate solution for the VCO frequency error problem. The circuit uses an analog clamp 15, which is difficult to optimize across a wide range of frequencies at the output. Also, the voltages presented by the clamp 15 are difficult to control.